With the scaling of MOSFET feature size, the requirements for the gate insulated isolation effect and the control ability of gate to channel region gets higher and higher. The conventional silicon oxide insulation layer could not continuously provide enough insulated isolation when its depth becomes thinner gradually, while the polysilicon gate could not precisely control the work function to adjust the device threshold voltage. Currently the high k-metal gate structure, which uses high k materials as gate insulation layer and filled metal materials as gate conductive layer, becomes the mainstream in MOSFET. Because the high k materials can easily react at high temperatures or under ion bombardment, the development of gate-first process, in which the gate stack structure is deposited first and then the S/D region is formed by ion implantation and activation annealing, is restricted. The gate-last process, in which a dummy gate stack is deposited first and the S/D region is formed by ion implantation, and then the dummy gate is etched to form gate trench and the gate stack is deposited in the gate trench, gradually dominates.
However, with further decrease in size, the aspect ratio of the gate trench becomes bigger continuously for smaller device. The gate trench filling in gate-last process becomes a major bottleneck in process development. As disclosed in the US 2012/012948 A1, because the width of the gate trench is too narrow compared to its depth, the first layer metal materials will form a “overhang” at the top edge of the gate trench when depositing the work function adjusting layer/metal blocking layer, i.e. the first metal layer will form a local protrusion that is toward the gate trench center and beyond the gate spacer at the top edge. The second layer metal materials will close and end deposition filling earlier due to this local protrusion in the subsequent metal filling layer deposition, and accordingly form voids caused by incompletely filling in the middle and bottom parts. These voids cause unnecessary increase in metal gate resistance and lower the device performance.